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AHB-Multilayer

Unified Chip Design Platform - AMBA - AHB Multilayer.

Classes:

Name Description
Master

Master.
Slave

Slave.
AhbFsmMlType

FSM Type for AHB Multilayer.
UcdpAhbMlMod

AHB Multilayer.
UcdpAhbMlExampleMod

Just an Example Multilayer.

Master

Bases: AddrMaster

Master.

Attributes:

Name Type Description
proto AmbaProto

Protocol Version.

proto instance-attribute 

proto

Protocol Version.

Slave

Bases: AddrSlave

Slave.

Attributes:

Name Type Description
proto AmbaProto

Protocol Version.

proto instance-attribute 

proto

Protocol Version.

AhbFsmMlType

Bases: AEnumType

FSM Type for AHB Multilayer.

UcdpAhbMlMod

Bases: ATailoredMod, AddrMatrix

AHB Multilayer.

Multilayer.

Methods:

Name Description
add_master

Add master port named name connected to route.
add_slave

Add APB Slave.
build_top

Build example top module and return it.
get_overview

Matrix Overview.

Attributes:

Name Type Description
proto AmbaProto

Default Protocol.
is_sub bool

Full Address Decoding By Default.

proto class-attribute instance-attribute 

proto = AMBA3

Default Protocol.

is_sub class-attribute instance-attribute 

is_sub = False

Full Address Decoding By Default.

add_master 

add_master(name, slavenames=None, proto=None, route=None)

Add master port named name connected to route.

Parameters:

Name Type Description Default
name str

Name or Pattern ('*' is supported)

 required

Other Parameters:

Name Type Description
slavenames Names | None

Names of slaves to be accessed by this master.
proto AmbaProto | None

Protocol.
route Routeable | None

port to connect this master to.

add_slave 

add_slave(
    name,
    baseaddr=AUTO,
    size=None,
    proto=None,
    masternames=None,
    route=None,
    ref=None,
)

Add APB Slave.

Parameters:

Name Type Description Default
name str

Slave Name.

 required

Other Parameters:

Name Type Description
baseaddr int | str

Base address, Next Free address by default. Do not add address space if None.
size Bytes | None

Address Space.
proto AmbaProto | None

AMBA Protocol Selection.
masternames Names | None

Names of masters to be accessed by this slave.
route Routeable | None

APB Slave Port to connect.
ref BaseMod | str | None

Logical Module connected.

build_top staticmethod 

build_top(**kwargs)

Build example top module and return it.

get_overview 

get_overview()

Matrix Overview.

UcdpAhbMlExampleMod

Bases: AMod

Just an Example Multilayer.

>>> print(UcdpAhbMlExampleMod().get_inst('u_ml').get_overview())
| Master > Slave | ram | periph | misc |
| -------------- | --- | ------ | ---- |
| ext            | X   |        | X    |
| dsp            | X   | X      |      |
<BLANKLINE>
<BLANKLINE>
<BLANKLINE>
* Top:     `None`
* Defines: `None`
* Size:    `3932320 KB`
<BLANKLINE>
| Addrspace | Type     | Base         | Size                        | Infos | Attributes |
| --------- | -------- | ------------ | --------------------------- | ----- | ---------- |
| reserved0 | Reserved | `0x0`        | `536870912x32 (2 GB)`       |       |            |
| misc      | Slave    | `0x80000000` | `5888x32 (23 KB)`           |       |            |
| reserved1 | Reserved | `0x80005C00` | `469756160x32 (1834985 KB)` |       |            |
| ram       | Slave    | `0xF0000000` | `16384x32 (64 KB)`          |       |            |
| periph    | Slave    | `0xF0010000` | `16384x32 (64 KB)`          |       |            |
| misc      | Slave    | `0xF0020000` | `8192x32 (32 KB)`           |       |            |
| reserved2 | Reserved | `0xF0028000` | `67067904x32 (261984 KB)`   |       |            |
<BLANKLINE>